Topic of the
PhD Thesis:
Sustainable development of digital circuits and systems: Taking planetary
boundaries into account
Key Words : Sustainability, Planetary boundaries, Digital systems, Integrated circuits
Context
Technological developments in the electronics sector are progressing at a very rapid pace, while concerns
about their environmental impacts are becoming increasingly prominent. Despite this growing awareness,
most existing approaches in electronics design still focus on relative impact reductions, such as improving
energy efficiency or optimizing resource use. While necessary, these approaches do not guarantee that
electronic systems operate within the limits of planetary boundaries.
In this context, the concept of absolute sustainability is emerging as a crucial framework to guide the future
development of electronic systems, by explicitly considering the Earth’s carrying capacities and equitable
sharing of resources.
Summary of the Thesis Topic
This PhD thesis aims to address key scientific challenges related to the integration of absolute sustainability
into the electronics sector. In particular, it will investigate how carrying capacities and sharing principles—
central concepts of absolute sustainability—can be identified for electronics and consistently translated from
the global scale down to the levels of digital systems and integrated circuits. Another core question is how
planetary boundaries can be concretely incorporated into system- and circuit-level design methodologies.
The main objective of the thesis is to move beyond relative environmental impact reduction and toward
electronic designs that are fully compatible with planetary boundaries. To achieve this, the work will define
socio-technical scenarios to derive sharing principles, perform one of the first absolute life cycle assessments
of a digital system, and propose a pioneering circuit design based on absolute environmental limits. This
research aims to lay foundational methodological and technological elements for truly sustainable
development of electronics.
Research environment:
This thesis will be hosted in the LSTA Laboratory from the CEA, in the DRT/LIST/DSCIN division.
The CEA (French Commission for Atomic and Renewable Energy) is a public research institute. It plays an
important role in the research, development and innovation community. The CEA has four missions: security
and defense, nuclear energy (fission and fusion), technology research for industry and fundamental research.
With 16 000 employees, including technicians, engineers, researchers and support personnel, the CEA is
involved in numerous research projects in collaboration with both academic and industrial partners.
In the section of the CEA focused on technology research for industry, the LIST institute is focused on
intelligent digital systems. This institute has a culture of innovation and has as a mission to transfer these
technologies to industrial partners. The DSCIN division specializes in complex digital and embedded systems
for AI, High-Performance Computing and Cyber security applications.
The focus of the LSTA laboratory is on the design and implementation of high-performance multi-core
architectures and accelerators. These systems are built using the latest technologies including advanced CMOS
(7 nm), 2.5D/3D integration, non-volatile memories and FPGAs. These systems are used for High Performance
Computing (HPC) applications, AI (Artificial Intelligence) applications and quantum computing (digital control
of quantum CMOS circuits). This laboratory is located in Grenoble.
For the academic registration, the candidate will be affiliated with the doctoral school I-MEP². The school is
located in the Grenoble region. It is one of the 13 doctoral schools of the Doctoral College within the University of Grenoble Alpes.
Contacts
Supervisor: Chiara Sandionigi Email: chiara.sandionigi@cea.fr
Directory Maud Rio UGA/G-SCOP
Email: maud.rio@g-scop.eu
Qualifications : Master’s degree in computer science or electronics. Knowledge of development of
architectures for integrated circuits. Knowledge of Life Cycle Analysis and eco-design
will be highly appreciated.
To Apply : Please send your application to Chiara Sandionigi and Maud Rio including:
- A detailed CV
- A cover letter
- Marks and ranking for the three previous academic years
- Contact information for two references
Contact : Chiara Sandionigi
CEA DRT/LIST/DSCIN/LSTA
CEA, Institut List, Campus Minatec
17 avenue des Martyrs, F-38054 Grenoble Cedex
Telephone: +33 (0)4 38 78 95 77
Email: chiara.sandionigi@cea.fr
More information on : http://www-instn.cea.fr/
Start and End Dates Octobre 2026 – Octobre 2029